`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/06/23 20:38:50
// Design Name: 
// Module Name: add_sub_4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module add_sub_4(
    input clk,
    input clr_n,
    input wire [3:0] a,
    input wire [3:0] b,
    input wire control, 
    

    output wire[6:0] a_to_g,
    output wire[3:0] an,
    

    output wire [3:0] result_tens_bcd,
    output wire [3:0] result_units_bcd
);


    // 1. 将输入a, b从二进制转换为BCD码 

    reg [3:0] a_tens, a_units;
    reg [3:0] b_tens, b_units;
    integer i;
  always @(*) begin
    // a 拆位
    
    // 使用多个比较器拆分a的十位和个位
    if (a >= 10) begin
        a_tens = 1;
        a_units = a - 10;
    end


    // 使用多个比较器拆分b的十位和个位
    if (b >= 10) begin
        b_tens = 1;
        b_units = b - 10;
    end
end


    // 2. 加法

    wire [3:0] add_tens, add_units;
    wire       add_cf;
    
    wire [4:0] units_sum;
    wire [4:0] tens_sum;
    wire       units_carry;

    assign units_sum = a_units + b_units;
    assign units_carry = (units_sum > 9);
    assign add_units = units_carry ? (units_sum - 10) : units_sum[3:0];

    assign tens_sum = a_tens + b_tens + units_carry;
    assign add_cf = (tens_sum > 9);
    assign add_tens = add_cf ? (tens_sum - 10) : tens_sum[3:0];


    // 3. 减法
    reg [6:0] sub_s_abs_value;           // 假设值范围 0~99
    reg [3:0] sub_tens, sub_units;
    wire       sub_cf;

    wire [4:0] sub_c_internal; 
    wire [3:0] sub_bx_internal;
    wire       sub_is_negative;
    wire [3:0] sub_s_abs_value;
    
    assign sub_bx_internal = b ^ {4{1'b1}}; 
    assign sub_c_internal[0] = 1'b1;       
    assign sub_s = a ^ sub_bx_internal ^ sub_c_internal[3:0];
    

    assign sub_c_internal[4:1] = (a[3:0] & sub_bx_internal[3:0]) | (sub_c_internal[3:0] & (a[3:0] ^ sub_bx_internal[3:0]));
    
    assign sub_cf = sub_c_internal[4];
    assign sub_is_negative = (sub_cf == 0);
     
    

  integer temp;
   reg [3:0] sub_units_left;
always @(*) 
begin
    sub_s_abs_value = sub_is_negative ? (~sub_s + 1) : sub_s;
    temp = sub_s_abs_value;
    sub_tens = 0;
end
always @(*) 
begin
    // 第一个比较器：判断是否大于等于 30
    if (sub_units >= 30) begin
        sub_tens = 3;
        sub_units_left = sub_units - 30;
    end
    // 第二个比较器：判断是否大于等于 20
    else 
    if (sub_units >= 20) begin
        sub_tens = 2;
        sub_units_left = sub_units - 20;
    end
    // 第三个比较器：判断是否大于等于 10
    else if (sub_units >= 10) begin
        sub_tens = 1;
        sub_units_left = sub_units - 10;
    end
    sub_units_left = sub_units;
end
    

    

    assign result_tens_bcd = control ? sub_tens : add_tens;
    assign result_units_bcd = control ? sub_units_left : add_units;


    wire [15:0] x;
    assign x = {a_tens, a_units, b_tens, b_units};
    
    x7seg x1(
        .x(x), .clk(clk), .clr_n(clr_n), .a_to_g(a_to_g), .an(an)
    );
    
endmodule








